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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRBPTR_EL1, Trace Buffer Write Pointer Register</h1><p>The TRBPTR_EL1 characteristics are:</p><h2>Purpose</h2>
        <p>Defines the current write pointer for the trace buffer.</p>
      <h2>Configuration</h2><p>External register TRBPTR_EL1 bits [63:0] are architecturally mapped to AArch64 System register <a href="AArch64-trbptr_el1.html">TRBPTR_EL1[63:0]</a>.</p><p>TRBPTR_EL1 is in the Core power domain.
    </p><p>This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBPTR_EL1 are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>TRBPTR_EL1 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_0">PTR</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_0">PTR</a></td></tr></tbody></table><h4 id="fieldset_0-63_0">PTR, bits [63:0]</h4><div class="field"><p>Trace Buffer current write pointer address.</p>
<p>Defines the virtual address of the next entry to be written to the trace buffer.</p>
<p>If <a href="AArch64-pmbidr_el1.html">PMBIDR_EL1</a>.Align is not zero, then it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether bits [M-1:0] are <span class="arm-defined-word">RES0</span> or read/write, where M is an integer between 1 and <a href="AArch64-pmbidr_el1.html">PMBIDR_EL1</a>.Align inclusive.</p>
<p>The architecture places restrictions on the values that software can write to the pointer. For more information see <span class="xref">'Restrictions on Programming the Trace Buffer Unit'</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing TRBPTR_EL1</h2>
        <p>The PE might ignore a write to TRBPTR_EL1 if any of the following apply:</p>

      
        <ul>
<li><a href="ext-trblimitr_el1.html">TRBLIMITR_EL1</a>.E == <span class="binarynumber">0b1</span> and the Trace Buffer Unit is using Self-hosted mode.
</li><li><a href="ext-trblimitr_el1.html">TRBLIMITR_EL1</a>.XE == <span class="binarynumber">0b1</span> and the Trace Buffer Unit is using External mode.
</li></ul>
      <h4>TRBPTR_EL1 can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>TRBE</td><td><span class="hexnumber">0x008</span></td><td>TRBPTR_EL1</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalTraceBufferAccess(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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